April 20, 2005
Super B Factory Workshop, Hawaii
Peter Križan, Ljubljana
Read-out electronics: ASIC under development
–Gain：5 [V/pC]
–Shaping time：0.15 [μs]
–S/N     ：8 (@2000[e])
–Readout ：pipeline with shift register
–Package : 18 channels/chip
•
□4.93[mm]
Preamp
Shaper
VGA
Comparator
Shift register
Need high density front-end electronics.     Need high gain with very low noise amplifiers. Deadtimeless readout scheme-> Pipeline.
Develop an ASIC for the front-end electronics