//
//  File : camac_event_flat3.c
//  ( collector for flatpanelPMT )
//  Description : event handler for collector in UNIDAQ
//
//  Author : T.Matsumoto
//  Date   : 2003/06/28
//
//  Modified: 2004/02/28
//  By      : S.Korpar & A.Gorisek

#include "camlib.h"
#include <errno.h>
#include <stdio.h>

#include <sys/types.h>
#include <sys/fcntl.h>
#include <sys/mman.h>
#include <sys/vme_types.h>
#include <sys/vme_debug.h>
#include <sys/vme.h>
#include <sys/time.h>
#include <time.h>


//#define TEST
#define ORIG
#define INCLUDE_CAMAC
//#define TEST_TDC_BUFFERING
#define TEST_ADC_CLEAR
#define TEST_SCALER

#ifdef ORIG
#  define WWHILE weight_while(0) 
#else
#  define WWHILE
#endif

#define LOOP_WAIT_CNT 200 //time-out delay
#define TIMEOUT 60

#define DATA_UNIT_SIZE 1
//#define DATA_UNIT_SIZE sizeof(int)

// CAMAC
#define INTREG 4
#define ENABLE_INTREG (1 << (INTREG - 1))
#define OUTREG 5
#define ADC 6
#define TDC_KAIZU1 7
#define TDC_KAIZU2 8
#define TDC2277_RICH2_N 6
#define TDC2277_RICH2B 12
#define TDC2277_RICH2E TDC2277_RICH2B+TDC2277_RICH2_N-1
#define TDC2277_MCP_N 2
#define TDC2277_MCPB 10
#define TDC2277_MCPE TDC2277_MCPB+TDC2277_MCP_N-1
#define TDC2277_MWPC 18
#define SCALER 23
#define SCALER_NCH 4
// ================
// LeCroy 2277 status word 01111 1100 0000 0000
#define LC2277_CSTOP_BOTHEDGE 0x7c00
int status_tdc2277 = LC2277_CSTOP_BOTHEDGE;

#define MAX_MWPC_BUFFSIZ 32*16
#define MAX_TDC_BUFFSIZ TDC2277_RICH2_N*32*16


// VME
#define A_INT 0x2000
#define A_ADC 0x1000
#define S_INT 0x10
#define S_ADC 0x20
#define A16D16 "/dev/vme16d16"
size_t          size_adc=S_ADC;
unsigned long   addr_adc=A_ADC;
caddr_t         ptr_adc;
unsigned short  *wp_adc;
size_t          size_interrupt=S_INT;
unsigned long   addr_interrupt=A_INT;
caddr_t         ptr_interrupt;
unsigned short  *wp_interrupt;
int             fd; //a16d16 mem space  
// =================

// event counters
int  nall;
int  npass;

int ntotal_event;
int ntotal_rich1;
int ntotal_rich1_noshift;
// =================

FILE  *FileLog;

long  runtime, runutime;
long  start_runtime, start_runutime;
long  stop_runtime, stop_runutime;




int error_exit(int status) {
  //perror(strerror(status));
  exit(status);
}


// ----------------------
// camac initialization
// ----------------------
int camac_init( max_lengthP )
     /* arg */
     int *max_lengthP;  /* max length in 4 byte words for event */
{
  /* main */ 
  *max_lengthP = 100000;   
  
  nall  =  0;
  npass =  0;
  
  printf("camac_init: done!\n" );  
  return 0;
}

// -----------------------
//  camac event function
// -----------------------
int camac_event(mode,max_length,event_length,buf)
     /* arg */
     int *mode;
     int *event_length;
     int *max_length;
     short *buf;
{
  int status, i, q, x;
  int len, sn ;
  
  int count_rich1, count;
  
  int flag;
  int flag_shift ;
  
  unsigned short adc_flag;
  unsigned short raw_adc0[256], raw_adc1[256], raw_adc2[256], raw_adc3[256];
  int adc0[256], adc1[256], adc2[256], adc3[256];

#ifdef TEST_SCALER
  unsigned short sc_data[SCALER_NCH];
#endif
  
  int data;
  
  int ch, tmp;
  
#ifdef INCLUDE_CAMAC
  int lam_flag = 0;
  // bit1  : TDC KAIZU (1st)
  // bit2  : TDC KAIZU (2nd)
  // bit3  : Lecroy ADC 1
  // bit4  : Lecroy ADC 2
  // bit5  : TDC2277(MCP)   (1st)
  // bit6  : TDC2277(MCP)   (2st)
  // bit7  : TDC2277(RICH2) (3rd)
  // bit8  : TDC2277(RICH2) (4th)
  // bit9  : TDC2277(RICH2) (5th)
  // bit10 : TDC2277(RICH2) (6th)
  // bit11 : TDC2277(RICH2) (7th)
  // bit12 : TDC2277(RICH2) (8th)
  // bit13 : TDC2277(RICH2) (MWPC)

  int nhits_mwpc=0, nhits_mcp=0, nhits_rich2=0;
  
  int t1_tdc = 0, t2_tdc = 0, t3_tdc = 0;
  int t1_adc = 0, t2_adc = 0, t3_adc = 0;
  int p1v_tdc = 0, p1h_tdc = 0, p2v_tdc = 0, p2h_tdc = 0;
  int p1v_adc = 0, p1h_adc = 0, p2v_adc = 0, p2h_adc = 0;
  int gc1_tdc = 0, gc2_tdc = 0;
  int gc1_adc = 0, gc2_adc = 0;
  int ac_tdc = 0, ac_adc = 0;
  int aw1_tdc = 0, aw2_tdc = 0;
  int aw1_adc = 0, aw2_adc = 0;
  
  int rawtdc_mwpc[MAX_MWPC_BUFFSIZ];
  int ch_phase_mwpc[MAX_MWPC_BUFFSIZ];
  int tdc_mwpc[MAX_MWPC_BUFFSIZ];

  int rawtdc_rich2[MAX_TDC_BUFFSIZ];
  int ch_phase_rich2[MAX_TDC_BUFFSIZ];
  int tdc_rich2[MAX_TDC_BUFFSIZ];

  int rawtdc_mcp[MAX_TDC_BUFFSIZ];
  int ch_phase_mcp[MAX_TDC_BUFFSIZ];
  int tdc_mcp[MAX_TDC_BUFFSIZ];
#endif


#ifdef ORIG
  // output register level off ( ch1 );
  // clear SW veto ( confirmation )
  *(wp_interrupt+5) &= 0xffff - 1<<0;
  WWHILE;
#endif
  
  /* main */
  *event_length = 0;
  while(*event_length==0 ){
    
#ifdef INCLUDE_CAMAC
    // -----CAMAC initialization-----
    
    // system clear 
    CAMAC(NAF(TDC_KAIZU1,0, 9),&i,&q,&x); 
    CAMAC(NAF(TDC_KAIZU2,0, 9),&i,&q,&x); 
    CAMAC(NAF(ADC,0, 9),&i,&q,&x); 
    
    sn = TDC2277_MWPC;
    CAMAC(NAF(sn, 0,  9), &i, &q, &x); 
    for ( sn = TDC2277_MCPB; sn <= TDC2277_MCPE;sn++ ){
      CAMAC(NAF(sn, 0,  9), &i, &q, &x); 
    }
    for ( sn = TDC2277_RICH2B; sn <= TDC2277_RICH2E;sn++ ){
      CAMAC(NAF(sn, 0,  9), &i, &q, &x); 
    }

    // clear LAM
    CAMAC(NAF(INTREG,0, 9),  &i, &q, &x );   
    // enable LAM
    CAMAC(NAF(INTREG, 0, 26),  &i, &q, &x ); 
    
    CAMAC(NAF(TDC_KAIZU1,0, 26),&i,&q,&x); 
    CAMAC(NAF(TDC_KAIZU2,0, 26),&i,&q,&x); 
    CAMAC(NAF(ADC,0, 26),&i,&q,&x); 
    
    sn = TDC2277_MWPC;
    CAMAC(NAF(sn, 0,  26), &i, &q, &x); 
    for ( sn = TDC2277_MCPB; sn <= TDC2277_MCPE;sn++ ){
      CAMAC(NAF(sn, 0,  26), &i, &q, &x); 
    }
    for ( sn = TDC2277_RICH2B; sn <= TDC2277_RICH2E;sn++ ){
      CAMAC(NAF(sn, 0,  26), &i, &q, &x); 
    }
#endif

    // -----VME initialization-----
    // interrupt register
    *(wp_interrupt + 6 ) = 0;
    WWHILE;
    *(wp_interrupt + 6 ) |= 1<<1;  // clear
    WWHILE;
    *(wp_interrupt + 6 ) |= 1<<4;  // enable 
    WWHILE;
    *(wp_interrupt + 6) |= (1<<3); // set mask
    WWHILE;
    
#ifdef TEST
    // output register level off ( ch1 );
    // clear SW veto
    *(wp_interrupt+5) &= 0xffff - 1<<0;
    WWHILE;
#endif
    
    // wait busy signal for VME interrupt
    while( (*(wp_interrupt+6)&(1<<5)) == 0 ) WWHILE;

    
#ifdef TEST_ADC_CLEAR
    raw_adc0[0] = *(wp_adc+11);
    WWHILE;
#endif
    
    
#ifdef TEST
    // output register level on ( ch1 );
    // set SW veto
    *(wp_interrupt+5) |= 1<<0;
    WWHILE;
#endif

    // ---- VME ADC -----

    // read data
    flag = 0;
    count_rich1 = 0;
    while(1){
      
      count = 0;
      while(1){
	adc_flag = *(wp_adc+1);
	WWHILE;
	count += 1;
	if ( adc_flag & (1<<8) ) break; 
	
	if ( count>LOOP_WAIT_CNT ) { flag=1;break; }
      }
      
#ifdef TEST //test pulse-signals
      if (count_rich1==255) {
	*(wp_interrupt+4) = 1<<4 ;
        WWHILE;
      }
      *(wp_interrupt+4) = 1<<3 ;
      WWHILE;
#endif
      if (flag) break; 
      
      
      raw_adc0[count_rich1] = *(wp_adc + 8 + 0); //4th ADC ch 
      raw_adc1[count_rich1] = *(wp_adc + 8 + 1); //5th ADC ch
      raw_adc2[count_rich1] = *(wp_adc + 8 + 2); //6th ADC ch
      raw_adc3[count_rich1] = *(wp_adc + 8 + 3); //7th ADC ch
      
      WWHILE;
      
      count_rich1 += 1; //no. pmt read-out/ch.
      if ( count_rich1 == 256 ) break;
    }
  
    if ( count_rich1 == 256 ){
    
      for( len = 0; len<256; len++ ){
	adc0[len] = (*(short *)&(raw_adc0[len]))/0x10 ;
	adc1[len] = (*(short *)&(raw_adc1[len]))/0x10 ;
	adc2[len] = (*(short *)&(raw_adc2[len]))/0x10 ;
	adc3[len] = (*(short *)&(raw_adc3[len]))/0x10 ;
      }
    
#ifdef INCLUDE_CAMAC
      // Wait LAM for CAMAC
      status = CAM_WaitLAM(TIMEOUT);
      if( status != 0 ){
	printf( "Timeout! status = %d\n", status );
      }
    
      // Read interrupt register 
#  ifdef ORIG
      status = CAMAC(NAF(INTREG,0,0), &i, &q, &x );

#    ifdef TEST
      printf ( ">>>>>>>>>> i %d q %d x %d\n", i,q,x );
#    endif
    
      if ( i!= 0 ){
#  endif
      
	// ----- TDC_KAIZU -----
	// test LAM
	CAMAC(NAF(TDC_KAIZU1,0, 8), &i, &q, &x);
	if ( q == 1 ) lam_flag |= 1<<0;
      
	CAMAC(NAF(TDC_KAIZU2,0, 8), &i, &q, &x);
	if ( q == 1 ) lam_flag |= 1<<1;
      
	// read data 
	CAMAC(NAF(TDC_KAIZU1,0,0),&t1_tdc,&q,&x);
	CAMAC(NAF(TDC_KAIZU1,1,0),&t2_tdc,&q,&x);
	CAMAC(NAF(TDC_KAIZU1,2,0),&t3_tdc,&q,&x);
      
	CAMAC(NAF(TDC_KAIZU1,3,0),&p1v_tdc,&q,&x);
	CAMAC(NAF(TDC_KAIZU1,4,0),&p1h_tdc,&q,&x);
	CAMAC(NAF(TDC_KAIZU1,5,0),&p2v_tdc,&q,&x);
	CAMAC(NAF(TDC_KAIZU2,0,0),&p2h_tdc,&q,&x);
      
	CAMAC(NAF(TDC_KAIZU2,1,0),&gc1_tdc,&q,&x);
	CAMAC(NAF(TDC_KAIZU2,2,0),&gc2_tdc,&q,&x);
      
	CAMAC(NAF(TDC_KAIZU2,3,0),&ac_tdc,&q,&x);
      
	CAMAC(NAF(TDC_KAIZU2,4,0),&aw1_tdc,&q,&x);
	CAMAC(NAF(TDC_KAIZU2,5,0),&aw2_tdc,&q,&x);
      
	// ----- Lecroy ADC -----
	// test LAM
	CAMAC(NAF(ADC, 0, 8), &i, &q, &x);
	if ( q == 1 ) lam_flag |= 1<<2;
      
      
	// read data
	CAMAC(NAF(ADC,0,0),&t1_adc,&q,&x);
	CAMAC(NAF(ADC,1,0),&t2_adc,&q,&x);
	CAMAC(NAF(ADC,2,0),&t3_adc,&q,&x);
      
	CAMAC(NAF(ADC,3,0),&p1v_adc,&q,&x);
	CAMAC(NAF(ADC,4,0),&p1h_adc,&q,&x);
	CAMAC(NAF(ADC,5,0),&p2v_adc,&q,&x);
	CAMAC(NAF(ADC,6,0),&p2h_adc,&q,&x);
      
	CAMAC(NAF(ADC,7,0),&gc1_adc,&q,&x);
	CAMAC(NAF(ADC,8,0),&gc2_adc,&q,&x);
      
	CAMAC(NAF(ADC,9,0),&ac_adc,&q,&x);
      
	CAMAC(NAF(ADC,10,0),&aw1_adc,&q,&x);
	CAMAC(NAF(ADC,11,0),&aw2_adc,&q,&x);
     
	// ----- TDC2277 -----
	// test LAM
	for ( sn=TDC2277_MCPB; sn<= TDC2277_MCPE;sn++){
	  CAMAC(NAF(sn, 0, 8), &i, &q, &x); 
	  if ( q == 1 ) lam_flag |= 1<<(4+sn-TDC2277_MCPB);
	}
	for ( sn=TDC2277_RICH2B; sn<= TDC2277_RICH2E;sn++){
	  CAMAC(NAF(sn, 0, 8), &i, &q, &x); 
	  if ( q == 1 ) lam_flag |= 1<<(6+sn-TDC2277_RICH2B);
	}
	CAMAC(NAF(TDC2277_MWPC, 0, 8), &i, &q, &x); 
	if ( q == 1 ) lam_flag |= 1<<12;
            
      
	// read data
	nhits_mwpc = 0;
	sn = TDC2277_MWPC;
	while(1) {
	  CAMAC(NAF(sn, 0, 0), &data, &q, &x); 

#  ifdef TEST_TDC_BUFFERING	
	  if (q == 0) {
	    // test buffering in progress
	    CAMAC(NAF(sn, 0, 27), &i, &q, &x); 
	    if (q == 1) continue;
	    break;
	  }
#  else
	  if ( q == 0 ) break;
#  endif
	
	  rawtdc_mwpc[nhits_mwpc] = data;        
	  nhits_mwpc++;
	
	}
      
	nhits_mcp = 0;
	for (sn = TDC2277_MCPB; sn <= TDC2277_MCPE; sn++) {
	
	  while(1) {
	    CAMAC(NAF(sn, 0, 0), &data, &q, &x); 
	  
#  ifdef TEST_TDC_BUFFERING	
	    if (q == 0) {
	      // test buffering in progress
	      CAMAC(NAF(sn, 0, 27), &i, &q, &x); 
	      if (q == 1) continue;
	      break;
	    }
#  else
	    if ( q == 0 ) break;
#  endif
	  
	    // for sequential channel number(0 - 191) 
	    data &= 0x03fffff;
	    data += (((sn - TDC2277_MCPB) * 32) << 17); 
	  
	    rawtdc_mcp[nhits_mcp] = data;        
	    nhits_mcp++; // MCP hits
	  }
	}
      
	nhits_rich2 = 0;
	for (sn = TDC2277_RICH2B; sn <= TDC2277_RICH2E; sn++) {
	
	  while(1) {
	    CAMAC(NAF(sn, 0, 0), &data, &q, &x); 
	  
#  ifdef TEST_TDC_BUFFERING	
	    if (q == 0) {
	      // test buffering in progress
	      CAMAC(NAF(sn, 0, 27), &i, &q, &x); 
	      if (q == 1) continue;
	      break;
	    }
#  else
	    if ( q == 0 ) break;
#  endif
	  
	    // for sequential channel number(0 - 191) 
	    data &= 0x03fffff;
	    data += (((sn - TDC2277_RICH2B) * 32) << 17); 
	  
	    rawtdc_rich2[nhits_rich2] = data;        
	    nhits_rich2++; // RICH2 hits
	  }
	}

#ifdef TEST_SCALER
	for ( ch=0; ch<SCALER_NCH; ch++ ) {
	  CAMAC(NAF(SCALER, ch, 0), &data, &q, &x);
	  sc_data[ch]=data ;

#  ifdef TEST
	  printf ( "evnt %d - sc_ch %d: %d\n",ntotal_event, ch, data ) ; 
#  endif

	}
#endif
	
      
	// unpacking data
	for(len=0;len< nhits_mwpc;len++){
	  ch_phase_mwpc[len]  = rawtdc_mwpc[len] & 0xffff0000; 
	  ch_phase_mwpc[len] >>= 16;
	  tdc_mwpc[len] = rawtdc_mwpc[len] & 0x00ffff; 
	}
      
	for(len=0;len< nhits_mcp;len++){
	  ch_phase_mcp[len] = rawtdc_mcp[len]  & 0xffff0000; 
	  ch_phase_mcp[len] >>= 16;
	  tdc_mcp[len] = rawtdc_mcp[len] & 0x00ffff; 
	}
	for(len=0;len< nhits_rich2;len++){
	  ch_phase_rich2[len] = rawtdc_rich2[len]  & 0xffff0000; 
	  ch_phase_rich2[len] >>= 16;
	  tdc_rich2[len] = rawtdc_rich2[len] & 0x00ffff; 
	}

#  ifdef ORIG
      }
#  endif
    
#endif
      
    
    
      // unpacking data
      //    if ( count_rich1 == 256 ) {
      *event_length = (50+2*(nhits_mwpc+nhits_mcp+nhits_rich2)+1024)*DATA_UNIT_SIZE;
      ntotal_rich1 +=1;
    }else{
      *event_length = (50+2*(nhits_mwpc+nhits_mcp+nhits_rich2))*DATA_UNIT_SIZE;
    }
    ntotal_event +=1;
      
#ifdef TEST
    if ( *event_length==((50+2*(nhits_mwpc+nhits_mcp+nhits_rich2)+1024)*DATA_UNIT_SIZE ) ) {
      printf ( " evnt:%4d size:%2d %5d %5d %5d %5d %5d %5d %5d %5d %5d\n",
	       ntotal_event, *event_length, 
	       raw_adc0[4], raw_adc0[5], raw_adc0[6], raw_adc0[7],
	       raw_adc0[8], raw_adc0[9], raw_adc0[10], raw_adc0[11],
	       raw_adc0[12] ) ;
    }
#endif
  }
    
    
  getusec(&runtime,&runutime);
    
  // ----- Data allocation ( Total 5170ch max) -----
  // - Monitoring ( total 10ch )
  //    0      : run time(sec)
  //    1      : RICH1 used #event
  //    2      : RICH1 used rate(%)
  //    3      : RICH1 no shifted rate (%)
  //    4      : #count for RICH1 ( VME ADC )
  //    5      : #hit for RICH2
  //    6      : #hist for MCP
  //    7      : #hit for MWPC
  //    8      : lam_flag
  //    9      : ADC shift flag
  //   10      : |ADC diff. | for shift search 
  //   11-19   : not used
  // - Trigger ( total 6ch )
  //   20      : T1 TDC (1ch)        12bit
  //   21      : T2 TDC (1ch)        12bit 
  //   22      : T3 TDC (1ch)        12bit 
  //   23      : T1 ADC (1ch)        10bit
  //   24      : T2 ADC (1ch)        10bit
  //   25      : T3 ADC (1ch)        10bit
  // - Positioning ( total 8ch )
  //   26      : P1V TDC (1ch)       12bit           
  //   27      : P1H TDC (1ch)       12bit           
  //   28      : P2V TDC (1ch)       12bit  
  //   29      : P2H TDC (1ch)       12bit  
  //   30      : P1V ADC (1ch)       10bit
  //   31      : P1H ADC (1ch)       10bit
  //   32      : P2V ADC (1ch)       10bit
  //   33      : P2H ADC (1ch)       10bit
  // - Gas Cherenkov ( total 4ch )
  //   34      : GC1 TDC (1ch)       12bit
  //   35      : GC2 TDC (1ch)       12bit
  //   36      : GC1 ADC (1ch)       10bit
  //   37      : GC2 ADC (1ch)       10bit 
  // - Aerogel Crehkov for proton veto ( total 2 ch )
  //   38      : AC TDC (1ch)        12bit
  //   39      : AC ADC (1ch)        10bit
  // - Aerogel Counter with Wavelength shifter ( total 4ch )
  //   40      : AW1 TDC (1ch)       12bit
  //   41      : AW2 TDC (1ch)       12bit
  //   42      : AW1 ADC (1ch)       10bit
  //   43      : AW2 ADC (1ch)       10bit
  //   44-47   : scaler counts
  //  - MCP   ( total 64ch x8(multihit)x3(ch,le,te) )
  //   50     : MCP TDC    16bit
  //  - RICH2 ( total 192ch x8(multihit)x3(ch,le,te) )
  //   50 + 2*nhits_mcp  : RICH2 TDC    16bit
  // - MWPC  ( total 10ch x8(multihit)x3(ch,le,te))
  //   50  + 2*(nhits_mcp + nhits_rich2)  : MWPC1, MWPC2 TDC   16bit
  // - RICH1 ( total 1024ch)         12bit
  //   50 + 2*(nhits_mcp + nhits_rich2 + nhits_mwpc) : RICH1 ADC(1024ch)
  // ----- Data allocation ( Total 1034ch, max ) -----
  
  buf[0] = runtime - start_runtime;
  buf[1] = ntotal_rich1;
  buf[2] = 100*ntotal_rich1/ntotal_event;
  buf[3] = 100*ntotal_rich1_noshift/ntotal_event;
  buf[4] = count_rich1;    

  tmp = adc1[218] - adc1[217];
  if ( tmp<0 ) tmp *= -1;
  if ( tmp<6 ) flag_shift = 0;
  else         flag_shift = 1;
  if ( flag_shift == 0 ) ntotal_rich1_noshift += 1;
  buf[9] = flag_shift;
  buf[10] = tmp;
    
    
#ifndef INCLUDE_CAMAC
  buf[5] = 0;
  buf[6] = 0;
  buf[7] = 0;
  buf[8] = 0;
#else
  buf[5] = nhits_mcp;             // hits in RICH2 BURLE MCP
  buf[6] = nhits_rich2; // hits in RICH2 HAMAMATSU PMT
  buf[7] = nhits_mwpc;
  buf[8] = lam_flag;
  
  buf[20]  = t1_tdc;
  buf[21]  = t2_tdc;
  buf[22]  = t3_tdc;
    
  buf[23]  = t1_adc;
  buf[24]  = t2_adc;
  buf[25]  = t3_adc;
    
  buf[26] = p1v_tdc;
  buf[27] = p1h_tdc;
  buf[28] = p2v_tdc;
  buf[29] = p2h_tdc;
    
  buf[30] = p1v_adc;
  buf[31] = p1h_adc;
  buf[32] = p2v_adc;
  buf[33] = p2h_adc;
    
  buf[34] = gc1_tdc;
  buf[35] = gc2_tdc;
    
  buf[36] = gc1_adc;
  buf[37] = gc2_adc;
    
  buf[38] = ac_tdc;
  buf[39] = ac_adc;
    
  buf[40] = aw1_tdc;
  buf[41] = aw2_tdc;
  buf[42] = aw1_adc;
  buf[43] = aw2_adc;

#ifdef TEST_SCALER
  for ( ch=0; ch<SCALER_NCH; ch++ ) {
    buf[44+ch] = sc_data[ch] ; 
  }
#endif
    
  for( len =0;len<nhits_mcp;len++){
    buf[50+ 0*nhits_mcp + len ] = ch_phase_mcp[len];
    buf[50+ 1*nhits_mcp + len ] = tdc_mcp[len];
  }   
  for( len =0;len<nhits_rich2;len++){
    buf[50+ 2*nhits_mcp + 0*nhits_rich2 + len ] = ch_phase_rich2[len];
    buf[50+ 2*nhits_mcp + 1*nhits_rich2 + len ] = tdc_rich2[len];
  }   
  for( len =0;len<nhits_mwpc;len++){
    buf[50 + 2*(nhits_mcp+nhits_rich2) +0*nhits_mwpc + len ] = ch_phase_mwpc[len];
    buf[50 + 2*(nhits_mcp+nhits_rich2) +1*nhits_mwpc + len ] = tdc_mwpc[len];
  }
#endif
  
  if ( count_rich1 == 256 ){
      
    for( len=0; len<256; len++){
      buf[50+2*(nhits_mwpc+nhits_rich2+nhits_mcp)+0*256+len] = 0x800 + adc0[len];
      buf[50+2*(nhits_mwpc+nhits_rich2+nhits_mcp)+1*256+len] = 0x800 + adc1[len];
      buf[50+2*(nhits_mwpc+nhits_rich2+nhits_mcp)+2*256+len] = 0x800 + adc2[len];
      buf[50+2*(nhits_mwpc+nhits_rich2+nhits_mcp)+3*256+len] = 0x800 + adc3[len];
    }
    
#ifdef TEST
    if ( *event_length==((50+2*(nhits_mwpc+nhits_rich2+nhits_mcp)+1024)*DATA_UNIT_SIZE) ) {
      printf ( " XXXX:%4d size:%2d %5d %5d %5d %5d %5d %5d %5d %5d %5d\n",
	       ntotal_event, *event_length, 
	       adc0[4], adc0[5], adc0[6], adc0[7],
	       adc0[8], adc0[9], adc0[10], adc0[11],
	       adc0[12] ) ;
    }

    printf ( "%d %d\t%d %d\t%d %d\t%d %d\t%d %d\t%d %d\t%d %d\t%d %d\t%d %d\t%d %d\t%d %d\t%d %d\t%d %d\t%d %d\t%d %d\t%d %d\t%d %d\t%d %d\n\n",
	     buf[20]  , t1_tdc,
	     buf[21]  , t2_tdc,
	     buf[22]  , t3_tdc,
	     buf[23]  , t1_adc,
	     buf[24]  , t2_adc,
	     buf[25]  , t3_adc,
	     buf[26] , p1v_tdc,
	     buf[27] , p1h_tdc,
	     buf[28] , p2v_tdc,
	     buf[29] , p2h_tdc,
	     buf[30] , p1v_adc,
	     buf[31] , p1h_adc,
	     buf[32] , p2v_adc,
	     buf[33] , p2h_adc,
	     buf[34] , gc1_tdc,
	     buf[35] , gc2_tdc,
	     buf[36] , gc1_adc,
	     buf[37] , gc2_adc );

#endif
  }
    
  if ( count_rich1 != 0 ){
    nall += 1;
    if ( count_rich1 == 256 ) npass += 1;
  }
    
#ifdef ORIG
  // output register level off ( ch1 );
  // clear SW veto
  *(wp_interrupt+5) &= 0xffff - 1<<0;
  WWHILE;
#endif
    
  // output register pulse on ( ch3, for scaler )
  *(wp_interrupt+4) = 1<<2;
  WWHILE;
    
  return (0);
}
  
// -----------------------
//  camac begin function
// -----------------------
void camac_begin(run_type,param)
     /* arg */
     int *run_type;
     int *param;
{   
  /* var */
  int status,q,x;
  int i, len, sn;
    
  /* main */
    
  printf( "camac begin..." );
    
  //  ----- Open and Initialization -----
  sleep(1);

  
#ifdef INCLUDE_CAMAC
  // ----- initialization -----
  // -for CAMAC
  status = CAMOPN();
  if (status) error_exit(status);
  printf("CAMOPN() : OK\n");

  CSETCR(0);
  CGENZ();
  CGENC();
  CREMI();
  
  // -for Interupt register
  CAMAC(NAF(INTREG,0, 9), &i, &q, &x ); // clear LAM
  CAMAC(NAF(INTREG,0,24), &i, &q, &x ); // disable LAM
  CAMAC(NAF(INTREG,0,11), &i, &q, &x ); // clear LAM Mask

  //scaler
#ifdef TEST_SCALER    
    CAMAC(NAF(SCALER,0, 9),&i,&q,&x); 
#endif
    

  // Enable LAM
  status = CAM_EnableLAM(ENABLE_INTREG); 
  if ( status ) error_exit(status);
  
  // set status register for TDC2277
  CAMAC(NAF(TDC2277_MWPC,0,17), &status_tdc2277, &q, &x );
  for( sn= TDC2277_MCPB; sn <= TDC2277_MCPE; sn++ ){
    CAMAC(NAF(sn,0,17), &status_tdc2277, &q, &x );
  }
  for( sn= TDC2277_RICH2B; sn <= TDC2277_RICH2E; sn++ ){
    CAMAC(NAF(sn,0,17), &status_tdc2277, &q, &x );
  }

  // Disable LAM
  //status = CAM_DisableLAM();
  //if (status) error_exit(status);
#endif

   
  // - for VME
  if((fd = open(A16D16, O_RDWR)) == -1 ){
    perror("open"); exit(1);
  }
    
  if((ptr_interrupt = mmap(0,
			   size_interrupt,PROT_WRITE|PROT_READ,MAP_SHARED,fd,addr_interrupt))
     == (caddr_t)-1){
    perror("mmap_interrupt"); exit(1);
  }
    
  if((ptr_adc = mmap(0,
		     size_adc,PROT_WRITE|PROT_READ,MAP_SHARED,fd,addr_adc))
     == (caddr_t)-1){
    perror("mmap_adc"); exit(1);
  }
    
  wp_interrupt = (unsigned short*) ptr_interrupt;
  wp_adc = (unsigned short*) ptr_adc;
    
  // Set VME ADC trigger ( Photo coupler )
  *(wp_adc + 1 ) = 1<<4;
  WWHILE;
    
  // interrupt register initialization
  *(wp_interrupt + 6 ) = 0;
  WWHILE;
    
  printf( "done!\n");
    
  return;
}
  
// ----------------------
//  camac_pause function
// ----------------------
void camac_pause(mode)

     /* arg */
     int *mode;
{ 
  /* var */
  int status;
  int len;
  int i,q,x;

  /* main */

  printf( "camac pause... ");

#ifdef INCLUDE_CAMAC
  /* desable lam */
  // for CAMAC
  status = CAM_DisableLAM(); if (status) error_exit(status);
#endif
  
  // for VME
  // output register off ( level )
  *(wp_interrupt + 5) = 0;
  WWHILE;

  // disable 
  *(wp_interrupt + 6) &= (0xffff - ( 1<<4 ));
  WWHILE;

  printf( "done!\n");

  return;

}

// -----------------------
//  camac_resume function
// -----------------------
void camac_resume(mode)
     /* arg */
     int *mode;
{  
  /* var */
  int i = 0;
  int q,x;
  int sn;
  int status; 

  /* main */

  getusec(&start_runtime,&start_runutime);

  ntotal_event = 0;
  ntotal_rich1 = 0;

  printf( "camac resume... " );

  // ----- initialization -----

#ifdef INCLUDE_CAMAC
  // ----- initialization -----
  // -for CAMAC
  CSETCR(0);
  CGENZ();
  CGENC();
  CREMI();
  
  // -for Interupt register
  CAMAC(NAF(INTREG,0, 9), &i, &q, &x ); // clear LAM
  CAMAC(NAF(INTREG,0,24), &i, &q, &x ); // disable LAM
  CAMAC(NAF(INTREG,0,11), &i, &q, &x ); // clear LAM Mask
  
  // Enable LAM
  status = CAM_EnableLAM(ENABLE_INTREG); 
  if ( status ) error_exit(status);
  
  // set status register for TDC2277
  CAMAC(NAF(TDC2277_MWPC,0,17), &status_tdc2277, &q, &x );
  for( sn= TDC2277_MCPB; sn <= TDC2277_MCPE; sn++ ){
    CAMAC(NAF(sn,0,17), &status_tdc2277, &q, &x );
  }
  for( sn= TDC2277_RICH2B; sn <= TDC2277_RICH2E; sn++ ){
    CAMAC(NAF(sn,0,17), &status_tdc2277, &q, &x );
  }
#endif

  // - for VME
  // Interupt register
  *(wp_interrupt+6) = 0;
  WWHILE;
  *(wp_interrupt+6) |= (1<<1); // clear
  WWHILE;
  *(wp_interrupt+6) &= ( 0xffff - (1<<4)); // disable
  WWHILE;
  *(wp_interrupt+6) |= (1<<3); // set mask
  WWHILE;
 
  // output register 
  *(wp_interrupt+5) = 0;
  WWHILE;
  *(wp_interrupt+5) = 1<<1; // level on, ch2 
  WWHILE;

  printf( "done!\n");

  return;
}

// --------------------
// camac end function
// --------------------
void camac_end(run_type)

     /* arg */
     int *run_type;
{     
  /* var */

  /*main */

  printf( "camac end... ");

  // ----- Termination -----

#ifdef INCLUDE_CAMAC
  // -for CAMAC
  CAM_DisableLAM(); 
  CAM_Close();
#endif

  // -for VME
  // interrupt register
  *(wp_interrupt + 5) = 0; // output register level off
  WWHILE;
  *(wp_interrupt+6) &= (0xffff - ( 1<<4 )); // disable
  WWHILE;
  *(wp_interrupt+6) =0;
  WWHILE;

  munmap(ptr_interrupt,size_interrupt);  // close

  // adc
  munmap(ptr_adc,size_adc); // close

  close(fd); // close VME

  getusec(&stop_runtime,&stop_runutime);

  FileLog = fopen( "logfile", "a" );
  fprintf(FileLog, "Run time (min.): %d\n", 
	  (stop_runtime - start_runtime)/60);
  fprintf(FileLog, "Total event    : %d\n", ntotal_event );
  fprintf(FileLog, "flat panel  used     : %d [ %d %% ]\n", 
	  ntotal_rich1 , 100*ntotal_rich1/ntotal_event);
  if ( stop_runtime - start_runtime != 0 ){
    fprintf(FileLog, "DAQ  rate      : %d Hz\n",
	    ntotal_event/(stop_runtime - start_runtime) );
  }
  fclose(FileLog);

  printf( "done!\n");
  
  return;
}


// ------------------
//  misc. functions
// ------------------
int weight_while(num)
     /* arg */
     int num;
{
  /* var */
  int i, tmp;

  /* main */
  for ( i =0; i <num; i++ ) tmp = 0;

}

int getusec(sec, usec)
     /* arg */
     long *sec,*usec;
{
  /* var */
  struct timeval tp;
  struct timezone tzp;

  /* main */
  gettimeofday(&tp, &tzp);
  *sec = tp.tv_sec;
  *usec = tp.tv_usec;
}