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Meisei board is controled through a VME module called DSP8230.
DSP8230 is 64-bit I/O board, and the VME access is done
with A16D16 mode.

(1) VME address

   ADR_VERSION = 0x00, // check board version; read only
   ADR_MODE1   = 0x02, // mode set register 1
   ADR_MODE2   = 0x04, // mode set register 2
   ADR_SPW     = 0x06, // strobe pulse width
   ADR_STATUS  = 0x08, // status
   ADR_RESET   = 0x0a, // software reset; write only
   ADR_IO1L    = 0x18, // I/O 1 lower 16 bit
   ADR_IO1H    = 0x1a, // I/O 1 higher 16 bit
   ADR_IO2L    = 0x1c, // I/O 2 lower 16 bit
   ADR_IO2H    = 0x1e, // I/O 2 higher 16 bit

  Assignment of I/O :
     I/O 1 lower  --> Read only. Used to read out the parameter.
     I/O 1 higher --> Read only. Used to read out the hit data.
     I/O 2 lower  --> Write only. Used to write the data (paramter etc.).
     I/O 2 higher --> Write only. Used to write the command.

  A program "hapd" is prepared to enable the access to the boards.

  % ./hapd d          <---- initialize the board.
  % ./hapd c value    <---- send command to the board
  % ./hapd h          <---- read out the hitdata
  % ./hapd r          <---- read out the data (parameter etc.)
  % ./hapd s          <---- check the status
  % ./hapd w value    <---- write the data (parameter etc.)

(2) Command

  In order to control the Meisei board, we need to send commands
  to the DSP8230 through I/O 2 higher port. Following commands are
  available.

    CMD_TEST              0x0000        test buffer
    CMD_RESET             0x0010        reset
    CMD_CLEAR             0x0020        clear
    CMD_NREP_HDREAD       0x0030        set the number of repetition
    CMD_DACCLRALL         0x0080        ----
    CMD_DACSET            0x0090 [*]    set DAC value
    CMD_ASIC_INITALL      0x0100        initialize all the ASIC
    CMD_ASIC_INIT         0x0200 [*]    initialize one ASIC
    CMD_ASIC_PRMSHIFT     0x0210        shift parameter values
    CMD_ASIC_PRMSET       0x0220 [*]    set ASIC register
    CMD_ASIC_PRMREADBACK  0x0230        readback
    CMD_CSR0              0x0240        set CSR0
    CMD_CSR1              0x0250        set CSR1

  command with [*] is effective to only one ASIC, where the
  ASIC ID should be added to the command value. For example,
  if you want to set the DAC value for chip 2, you need to
  send the command 0x0092.

  Here is the meanings of each command:

  (a) CMD_TEST
    You can access to the test buffer prepared in the FPGA for test.

    e.g.) ./hapd c 0x0000
          ./hapd w 0x1234     <---- write 0x1234 to the buffer
          ./hapd r            <---- read out the buffer (0x1234)

  (b) CMD_RESET
    Reset the FPGA. All the parameters are set to default values.

    e.g.) ./hapd c 0x0010

  (c) CMD_CLEAR
    Clear the counters and the veto flag in the FPGA.
    This command should be send for every event.

  (d) CMD_NREP_HDREAD
    Set how many times you read the hitdata for one event.
    This value should be an integer not less than 4.5 x #(chip).

    e.g.) ./hapd c 0x0030
          ./hapd w 5         <---- 5 access per event (1 chip).

  (e) CMD_DACSET  [*]
    Set the DAC value.

    e.g.) ./hapd c 0x0092
          ./hapd w 2048      <---- threshold of chip 2 is set to 0V.

  (f) CMD_ASIC_INITALL, CMD_ASIC_INIT
    Initialize chips.

  (g) CMD_ASIC_PRMSHIFT
    Shift the parameter values. See below.

  (h) CMD_ASIC_PRMSET
    Set the ASIC parameters. 

     e.g.)  ./hapd c 0x0210    <--- send the parameter values to FPGA
            ./hapd w 0x0404    <--- parameters
            ./hapd w 0x0404
            ....
            ./hapd w 0x0404    
            ./hapd c 0x0220    <--- send the parameter to CHIP 0.
            ./hapd c 0x0222    <--- send the parameter to CHIP 2.

  (i) CMD_ASIC_PRMREADBACK
     Read back the ASIC parameter. This command should be sent
     just after CMD_ASIC_PRMSET

      e.g.) ....
            ./hapd c 0x0220
            ./hapd c 0x0230
            ./hapd r
            ./hapd r
            ....
        
  (j) CMD_CSR0
      Set CSR0. The definition of CSR0 is
         { vetoen, selftrigger, chip_enable[7:0] }

         vetoen : If on, trigger signal is vetoed unless the clear
                  command is sent.
         selftrigger : 1 = ASIC trgout is used;  0 = external trigger is used
         chip_enable 

        e.g.) ./csr0.sh 0x2001

  (k) CMD_CSR1
      Set CSR1. The definition of CSR1 is
         { subdelay, delay1[1:0], trgdelay[3:0], 3'b000, halfcycle[4:0] }

         subdelay : should be 1 when halfcycle = 2
         delay    : should be 1 when halfcycle = 2
         trgdelay : delay between trigger and hold
         halfcycle : (half of) clock cycle 
                        2 : 8.25 MHz  ( 33 MHz / 2 / 2 )
                        3 : 5.50 MHz  ( 33 MHz / 3 / 2 )
                        4 : 4.13 MHz  ..
                        5 : 3.30 MHz
                        6 : 2.75 MHz
                        7 : 2.38 MHz
                        8 : 2.06 MHz
                       .....
                       16 : 1.03 MHz

        e.g.) ./csr0.sh 0x5902